1. Field of the Invention
The present invention particularly relates to a solid-state imaging apparatus that is widely employed for an image input device of a movable communication terminal such as a video camera, a digital still camera, an image scanner or a portable phone.
2. Description of the Related Art
Japanese Patent Application Laid-Open No. 2008-085994 (hereinafter, referred to as Patent Document 1) describes a method of suppressing disturbance noise from being superimposed on a signal in a solid-state imaging apparatus. The solid-state imaging apparatus includes: a pixel array in which a plurality of pixels is arrayed in a row direction and a column direction; a plurality of reading out circuits for reading out signals from the pixels for respective columns in the pixel array; and a control portion for controlling each of the plurality of reading out circuits. Each of the plurality of reading out circuits includes: a holding portion for holding a reference voltage supplied from an external side; an operational amplification portion for amplifying the signals from the pixels for the respective columns based on the reference voltage held in the holding portion; and a disconnection portion for electrically disconnecting the holding portion from the external side. The control portion controls the disconnection portion to electrically disconnect the holding portion from the external side when the operational amplification portion amplifies the signals from the pixels for the respective columns.
As described above, even when disturbance noise is mixed in the reference voltage supplied from the external side, the holding portion holds the reference voltage, and then is disconnected from the external side, whereby the disturbance noise is prevented from being input to the operational amplification portion.
The problem and the principle of solving means described in Patent Document 1 are briefly described. FIG. 11 is a structural diagram of the solid-state imaging apparatus described in Patent Document 1. FIG. 12 is a timing chart for reading out the signals.
At a time t0, a control line PSEL1 becomes High LEVEL, so that a MOS transistor 5105 is turned on. At substantially the same time, a control line PRES1 becomes Low LEVEL, so that a MOS transistor 5103 is turned off. Also at substantially the same time, a control signal PCVR becomes Low LEVEL, so that a MOS transistor 5045 is turned off. In addition, a control signal PC0R becomes High LEVEL, so that a MOS transistor 5041 is turned on. In this case, a gate of a MOS transistor 5104 is in a floating state, and a signal at the gate of the MOS transistor 5104 is input to a capacitor 5031 through a common vertical output line 5106 as a noise signal N of the pixel. It should be noted that, at this time, the MOS transistor 5041 is turned on.
After that, at a time t1, the control signal PC0R is set to be Low LEVEL, so that the MOS transistor 5041 is turned off, whereby the noise signal N is held in the capacitor 5031.
Next, at a time t2, a control signal PTX1 turns on a MOS transistor 5102. Then, an optical signal S that is photoelectrically converted by a photoelectric conversion unit 5101 is input to the gate of the MOS transistor 5104, and an S+N signal obtained by superimposing the optical signal S on the noise signal N of the pixel is input to the capacitor 5031 through the common vertical output line 5106. The S+N signal is clamped at the level of the noise signal N by the capacitor 5031, a vertical line amplifier 5040 and a switch 5041, and hence an S+N−N=S signal can be extracted. At the same time, a signal obtained by adding a gain G having a ratio of the capacitance of the capacitor 5031 to a capacitor 5042 to the optical signal S and superimposing the resultant signal on a reference voltage VREF, that is, a signal of G×S+VREF is output from the vertical line amplifier 5040.
Further, at a time t3, a MOS transistor 5032 is turned on, so that the output from the vertical line amplifier 5040 is written into a capacitor 5033, to thereby hold the signal of G×S+VREF obtained at the time t2.
Here, a solid line of VREF in FIG. 12 represents an ideal reference voltage, but in actuality, the reference voltage becomes a signal as indicated by a broken line in FIG. 12 due to the influence of disturbance noise. It is considered a case where the MOS transistor 5045, a capacitor 5046 and a control signal, such as the control signal PCVR, are not provided and the reference voltage VREF is directly input to a positive input terminal of the vertical line amplifier 5040. In this case, a differenceα−β between VREF+α at the time t0 and VREF+β at the time t4 is output from the vertical line amplifier 5040 as a noise signal. A signal that is actually held in the capacitor 5033 is G×(S+α−β)+VREF+β. The gain G is added to the difference α−β that is disturbance noise of the reference voltage VREF, so that noise is emphasized. The emphasized noise is generated for each row, and is visually observed as random noise in a lateral-line pattern. This noise is referred to as lateral line noise.
In Patent Document 1, the signal of the reference voltage VREF is synchronized with the control signal PCVR, and the signal held in the capacitor 5046 is input to the positive input terminal of the vertical line amplifier 5040. In this manner, even in a case where the disturbance noise as indicated by the broken line is mixed in the reference voltage VREF, the reference voltage VREF+α continues to be held in the capacitor 5046 from the time t0 to the time t4. Accordingly, a difference of the reference voltage VREF between the time t1 at which the noise signal N is held in the capacitor 5031 and the time t4 at which the signal of the vertical line amplifier 5040 is held in the capacitor 5033 is zero. For both the output from the vertical line amplifier 5040 and the signal held in the capacitor 5033, no gain is added to the disturbance noise mixed in the reference voltage VREF. Noise of a regulator that is provided on the external side and generates the reference voltage VREF is a conceivable cause of the disturbance noise described in Patent Document 1. Even in a case where the reference voltage VREF is generated on an internal side of a semiconductor chip on which the solid-state imaging apparatus is formed, noise similar to the above-mentioned disturbance noise occurs due to noise of an internal generator circuit, for example, the regulator.
However, with only the countermeasure described in Patent Document 1, noise is not sufficiently suppressed. It is considered a case where High LEVEL or Low LEVEL of the control lines PRES1(2), PTX1(2) and PSEL1(2) for controlling a pixel portion is unsettled due to noise. In this case, the respective control lines are capacitively coupled with a signal holding portion of the pixel portion via a gate capacitor and a parasitic capacitor of the MOS transistor 5104 that serves as the signal holding portion of the pixel portion, whereby noise is mixed in the signal holding portion of the pixel portion. In a case of reading out the signals as illustrated in FIG. 12, when noise of the signal holding portion of the pixel portion at the time t1 is denoted by A and noise of the signal holding portion of the pixel portion at the time t4 is denoted by B, the signal to be finally held in the capacitor 5033 is obtained as G×(S+A−B)+VREF. According to this expression, noise of the control lines is mixed in the signal holding portion of the pixel portion via the capacitive coupling, and a signal obtained by adding the gain G to a noise difference A−B between the time t1 and the time t4 appears in the capacitor 5033.
“Noise” that unsettles High LEVEL or Low LEVEL of the control lines PRES1(2), PTX1(2) and PSEL1(2) as described above is based on noise of the power sources of driving buffers for driving the control lines. The same problem arises whether the power sources are supplied from the external side of the semiconductor chip on which the solid-state imaging apparatus is formed or are generated on the internal side of the semiconductor chip.
The present invention has an object to provide a solid-state imaging apparatus that is capable of preventing the harmful influence of noise generated in a control line.